Wei Chen
Chairman of Thousandcore Technology
Dr. Chen Wei, an expert in large-scale models and AI chips, holds a senior position and serves as the Chairman of Qianxin Technology. He is a professional member of the Association for Computing Machinery (ACM) and the China Computer Federation (CCF). His research focuses on large-scale model architecture, sparse quantization compression and deployment acceleration, storage and computation integration, AI chips, and 3D Chiplet processors. His related technological achievements have been widely applied in well-known IDCs and internet enterprises. Dr. Chen Wei has previously served as the Chief Scientist of a well-known artificial intelligence (natural language processing) company, Vice Director of the Chinese Academy of Sciences (2012), and leader of multiple national science and technology major projects. He holds over 70 patents and software copyrights in China and the United States (approximately 50 of which are invention patents). He is the author of several books including "Essentials of Sora Large Model Technology: Principles, Key Technologies, Model Architecture, and Future Trends," "In-depth Analysis of GPT-4 Large Model," "Essentials of ChatGPT Large Model Technology: Development History, Principles, Detailed Technical Architecture, and Future Industry," and "Intelligent Connected Vehicles: Detailed Explanation of Laser and Visual SLAM."
Topic
Analysis of the Architecture of Large Video Models and Challenges in Chip-level Training Deployment
With the gradual maturity of model technologies such as Sora and Stable Video Diffusion, Video Large Models (VLMs) are combining with the short video industry and ushering in a new outbreak of opportunities, and will surely become a hotspot in the Internet and film industry. From the perspective of Video Large Models and World Models, this sharing introduces the basic architecture and key technologies (including NaViT and RADM) of video large models such as Sora and SVD; discusses the specific training process and deployment cost of video large models; analyses the training efficiency and landing challenges of video large models brought by Memory Wall and Communication Wall; and focuses on the arithmetic and chip-level training deployment of this kind of large sequence models, combining with specific projects. Chip-level training deployment, combined with specific projects to give a combination of hardware and software solutions and system experience. Outline: 1 Video big models and world models 2 Comparative analysis of Sora and other video big model architectures 3 Key technologies of video big model 4 Video big model training and deployment challenges 5 Big Sequence Model Training and Deployment Solution from Algorithm to Chip
